(1) Field of the Invention
The present invention relates to a semiconductor device and a fabrication method therefor, and more particularly to a vertical bipolar transistor and a fabrication method therefor.
(2) Description of the Related Art
In the bipolar transistor, it is known that, the thinner the base region film, the higher will be the cutoff frequency f.sub.T which can be regarded as a yardstick for the operation speed of the transistor. Also known is that, the smaller the transistor becomes, the smaller will be a parasitic capacitance, etc. resulting in a higher speed operation. As a method for forming a thin base region, an ion-implantation method is used, but there is a limit in making a shallow implantation of impurity ions. Also, in the ion-implantation method, it is necessary to eliminate changes in silicon lattice atoms caused by the implanted ions, that is, irregularities or imperfections in silicon single crystals. In an annealing step under high temperature heating, the implanted impurities are diffused. As a result, the base region becomes correspondingly thicker.
As a technique for forming a thin base region, a low temperature epitaxial growth method is known. One of the bipolar transistor fabrication methods utilizing such technique has been disclosed in Japanese Patent Application Kokai Publication No. Hei 4-330730, in which the inventor is the same as that of the present application.
FIG. 1 shows, in a diagrammatic sectional view, a construction of the bipolar transistor disclosed in the above publication. Such construction is as follows:
On a surface of a P.sup.- -type single crystal silicon substrate 201 having resistivity of 10.about.15 .OMEGA..multidot.cm, an N.sup.+ buried layer 202 having arsenic as impurities is selectively formed. A surface of this P.sup.- -type single crystal silicon substrate 201 is covered by an N.sup.- -type silicon epitaxial layer 203 having a thickness of about 0.4 .mu.m and an impurity concentration of about 1.times.10.sup.16 cm.sup.-3. Formed in the N.sup.- -type silicon epitaxial layer 203, using a known selective oxidation method, are element isolation field oxide films 204 and 204a which extend to the P.sup.- -type single crystal silicon substrate 201 or the N.sup.+ buried layer 202. The field oxide films 204 are to element-isolate respective adjacent bipolar transistors. One side of the N.sup.- -type silicon epitaxial layer 203 divided by the field oxide film 204a and surrounded by the field oxide film 204 is converted to an N.sup.+ -type collector lead-out region 205 by diffusion of phosphorus. The explanation has thus far covered the construction of the silicon substrate 206.
The upper surface of the silicon substrate 206 is covered by a silicon nitride film 207. In this silicon nitride film 207, an opening 214a which reaches the N.sup.+ -type collector lead-out region 205 and an opening 214b which reaches the N.sup.- -type silicon epitaxial layer 203 are provided. The opening 214a is covered or filled by an N.sup.+ -type polycrystalline silicon film 212 which is connected to the N.sup.+ -type collector lead-out region 205 so as to become a collector lead-out electrode. The upper surface of the silicon nitride film 207 at the periphery of the opening 214b is covered by the P.sup.+ -type polycrystalline silicon film 211 which has an overhang portion with a width D2 in the inner side of the opening 214b and which serves as a base lead-out electrode. The silicon nitride film 207 and the polycrystalline silicon films 211 and 212 are covered by a silicon oxide film 213. The side surface of the silicon oxide film 213 immediately above the opening 214b is coincident with the side surface of the overhang portion of the P.sup.+ -type polycrystalline silicon film 211, and these side surfaces are provided with a first insulating film spacer 215 constituted by a silicon oxide film.
The upper surface of the N.sup.- -type silicon epitaxial layer 203 which is exposed to the opening 214b is covered by the P-type single crystal silicon layer 221 which is an intrinsic base region, and the lower surface of the P.sup.+ -type polycrystalline silicon film 211 exposed to the overhang portion is covered by a P.sup.+ -type polycrystalline silicon film 222. These P-type single crystal silicon layer 221 and P.sup.+ -type polycrystalline silicon film 222 are those which have been selectively formed on the surfaces of the single crystal silicon layer and the polycrystalline silicon film by a low temperature epitaxial growth method. The upper surface of the P-type single crystal silicon layer 221 and the lower surface of the P.sup.+ -type polycrystalline silicon film 222 are connected with each other. The side surface and the lower surface of the first insulating film spacer 215 as well as a part of the upper surface of the P-type single crystal silicon layer 221 and a part of the side surface of the P.sup.+ -type polycrystalline silicon film 222 are covered by a second insulating film spacer 226. An air gap defined by the second insulating film spacer 226 is provided with an N-type single crystal silicon layer 227 which fills the air gap and covers the upper surface of the P-type single crystal silicon layer 221 thereby serving as an emitter region. In the silicon oxide film 213, there are provided openings that reach respectively to the P.sup.+ -type polycrystalline silicon film 211 and the N.sup.+ -type polycrystalline silicon film 212. On the upper surface of the silicon oxide film 213, there are provided a metal electrode 231 connected to the N-type single crystal silicon layer 227 and metal electrodes 232 and 233 connected respectively to the P.sup.+ -type polycrystalline silicon film 211 and the N.sup.+ -type polycrystalline silicon film 212 through the openings in the silicon oxide film 213. These metal electrodes 231, 232 and 233 are made of such metal as aluminum.
In the conventional bipolar transistor described above, although it is possible to form a film which is thin when compared with an intrinsic base region formed by the ion-implantation, there are problems as explained henceforth.
The first problem relates to a parasitic capacitance. Insulation between the P.sup.+ -type polycrystalline silicon film 211 which constitutes the base lead-out electrode and the N.sup.- -type silicon epitaxial layer 203 which constitutes a part of the collector region is made by the silicon nitride film 207. For making good connection between the P.sup.+ -type polycrystalline silicon film 211 and the P-type single crystal silicon layer 221 which is the intrinsic base region, it is not desirable that the thickness of the silicon nitride film 207 be thicker than the sum of the thickness of the P-type single crystal silicon layer 221 which is selectively epitaxially grown and the thickness of the P.sup.+ -type polycrystalline silicon film 222 which is selectively grown simultaneously with the P-type single crystal silicon layer 221. Where the P-type single crystal silicon layer 221 which is the intrinsic base region is made thin in order to enhance the cut-off frequency f.sub.T, the thickness of the silicon nitride film 207 must inevitably be made thin. As a result, the parasitic capacitance generated between the base region and the collector region increases thereby deteriorating transistor performances.
The second problem is with fabrication and relates to a problem involved in the selective epitaxial growth. As a preliminary step during such processes as the formation of the first insulating film spacer 215, the formation of the opening 214b, and the formation of the P-type single crystal silicon layer 221 which is the intrinsic base region, the silicon oxide film 213 and the P.sup.+ -type polycrystalline silicon film 211 at predetermined regions are removed by anisotropic etching. At this time, over-etching is made by taking into consideration the variations in the thicknesses of the P.sup.+ -type polycrystalline silicon film 211 and the variations in the anisotropic etching. Thus, the silicon nitride film 207 immediately under the P.sup.+ -type polycrystalline silicon film 211 is removed in a thickness on the order of 10.about.30 nm. Since the first insulating film spacer 215 is formed when underlying layer state is as above, the lower surface of this first insulating film spacer 215 results in being located at a position about 10 .about.30 nm below the lower surface of the P.sup.+ -type polycrystalline silicon film 211. Where the epitaxial growth is carried out under such state, there is an adverse effect to the growth of the P.sup.+ -type polycrystalline silicon film 222 which interconnects the P-type single crystal silicon layer 221 which is the intrinsic base region and the P.sup.+ -type polycrystalline silicon film 211 which is the base lead-out electrode, which leads to a possible failure in interconnection between them.
The second problem explained above becomes more serious when such layer as the intrinsic base region is formed by the growth of silicon/germanium. This is because the ratio of growth speeds between the polycrystalline silicon film and the single crystal layer during the growth becomes smaller than 1 with an increase in the mixed crystal ratio of germanium. For example, in the case of Si.sub.0.9 Ge.sub.0.1, such ratio (growth speed of the polycrystalline film/growth speed of the single crystal layer) is 1/5.about.1/4.